The latest PCI Express 6.0 interface allows for 64Gb/s of data transfer in a single channel.
CDCM9102 data sheet, product information and support | TI.com
What is PCI Express Clock gating?and is it worth keeping enabled? I have heard from quite a few people that keeping a number of these options enabled has caused Whea errors on
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PCI-e Reference Clock Measurement with Multiplexers
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PCI Express 3.0 needs reliable timing design - EDN Asia
18329 - Endpoint for PCI Express - What clock frequency must be used when implementing a PCI Express solution in a Xilinx device?